Design basis of combinational logic circuit 組合邏輯電路設(shè)計(jì)基礎(chǔ)
Combinational logic circuit 組合邏輯電路
Finally , we study two applications of bdd . the first one is the fault detect of combinational logic circuits 最后,研究了基于bdd的組合電路的故障檢測(cè)方法和基于bdd的網(wǎng)絡(luò)可靠度的計(jì)算方法等兩方面的應(yīng)用。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance 仿真實(shí)驗(yàn)結(jié)果證明了改進(jìn)演化算法對(duì)于實(shí)現(xiàn)函數(shù)級(jí)數(shù)字組合邏輯電路的硬件演化是可行的,并且提高了演化算法的演化效率和收斂性能。
Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co . and the detailed analyses of typical examples are also given 結(jié)合altera公司classicep610芯片的結(jié)構(gòu),研究了將演化算法應(yīng)用于函數(shù)級(jí)數(shù)字組合邏輯電路的硬件演化,并且對(duì)典型實(shí)例進(jìn)行了詳細(xì)分析。